CS 433

CS 433 - Computer System Organization

Spring 2026

TitleRubricSectionCRNTypeHoursTimesDaysLocationInstructor
Computer System OrganizationCS433S331405LCD31400 - 1515 T R  1304 Siebel Center for Comp Sci Nishil Talati
Computer System OrganizationCS433S431407LCD41400 - 1515 T R  1304 Siebel Center for Comp Sci Nishil Talati
Computer System OrganizationCSE422S331408LCD31400 - 1515 T R  1304 Siebel Center for Comp Sci Nishil Talati
Computer System OrganizationCSE422S431409LCD41400 - 1515 T R  1304 Siebel Center for Comp Sci Nishil Talati

Official Description

Computer hardware design and analysis and interface with software. Advanced processor design, including superscalar, out-of-order issue, branch prediction, and speculation. Memory hierarchy design, including advanced cache optimizations, main memory, and virtual memory. Principles of multiprocessor design, including shared-memory, cache coherence, synchronization, and consistency. Other advanced topics depending on time; e.g., GPUs and accelerators, warehouse computers and data centers, security. Course Information: Same as CSE 422. 3 undergraduate hours. 4 graduate hours. Prerequisite: CS 233.

Course Director

Text(s)

Computer Architecture: A Quantitative Approach, 6th Ed, by John L. Hennessy and David A. Patterson

Learning Goals

Understand design principles and methods used in contemporary processors and memory systems and apply them to new designs. (1), (2)
Evaluate the performance of a modern computer (1), (2)
Determine sources of potential performance bottlenecks in a processor design and determine techniques to address them. (1), (2)
Reason about sources of low memory system performance for a workload and determine techniques to address them (1), (2)
Evaluate tradeoffs between hardware and software techniques to achieve a performance goal (1), (2), (6)
Understand requirements for a correct parallel program and methods for supporting them in hardware. (1), (2), (6)

Topic List

Fundamental concepts related to performance, power, reliability, cost vs. price
Basic pipeline structure: some review from pre-requisite, multicyle functional units, static branch prediction, handling interrupts
Instruction-level parallelism: hardware techniques (e.g., dynamic scheduling, superscalar, dynamic branch prediction, handling precise interrupts)
Instruction-level parallelism: software-driven techniques (e.g., loop unrolling, trace scheduling, predication, memory access reordering)
Advanced concepts in cache design (e.g., prefetching, lockup-free caches, multilevel caches)
Main memory and virtual memory
Multiprocessors/multicore: parallelism models
Cache coherence: snoopy and directory solutions
Synchronization
Memory consistency models
Data parallel architectures

Required, Elective, or Selected Elective

Selected Elective.

Last updated

2/10/2019by Sarita V. Adve